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1 ? fn3182.6 ICL7665S cmos micropower over/under voltage detector the ICL7665S super cmos micropower over/under voltage detector contains two low power, individually programmable voltage detectors on a single cmos chip. requiring typically 3 a for operation, the device is intended for battery-operated systems and instruments which require high or low voltage warnings, settable trip points, or fault monitoring and correction. the trip points and hysteresis of the two voltage detectors are individually programmed via external resistors. an internal bandgap-type reference provides an accurate threshold voltage while operating from any supply in the 1.6v to 16v range. the ICL7665S, super programmable over/under voltage detector is a direct replacement for the industry standard icl7665b offering wider operating voltage and temperature ranges, improved threshold accuracy (ICL7665Sa), and temperature coefficient, and guaranteed maximum supply current. all improvements are highlighted in the electrical characteristics section. all critical parameters are guaranteed over the entire commercial and industrial temperature ranges. features ? guaranteed 10 a maximum quiescent current over temperature ? guaranteed wider operating voltage range over entire operating temperature range ? 2% threshold accuracy (ICL7665Sa) ? dual comparator with precision internal reference ? 100ppm/c temperature coeffi cient of threshold voltage ? 100% tested at 2v ? output current sinking ability . . . . . . . . . . . . up to 20ma ? individually programmable upper and lower trip voltages and hysteresis levels ? pb-free available applications ? pocket pagers ? portable instrumentation ? charging systems ? memory power back-up ? battery operated systems ? portable computers ? level detectors pinout ICL7665S (soic, pdip) top view ordering information part number temp. range (c) package pkg. dwg. # ICL7665Scba 0 to 70 8 ld soic (n) m8.15 ICL7665Scpa 0 to 70 8 ld pdip e8.3 ICL7665Sacba 0 to 70 8 ld soic (n) m8.15 ICL7665Sacbaz (note) 0 to 70 8 ld soic (n) (pb-free) m8.15 ICL7665Sacbaz-t (note) 0 to 70 8 ld soic (n) tape and reel (pb-free) m8.15 ICL7665Sacpa 0 to 70 8 ld pdip e8.3 ICL7665Siba -40 to 85 8 ld soic (n) m8.15 ICL7665Sipa -40 to 85 8 ld pdip e8.3 ICL7665Saiba -40 to 85 8 ld soic (n) m8.15 ICL7665Saipa -40 to 85 8 ld pdip e8.3 note: intersil pb-free products em ploy special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow te mperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020b. out 1 hyst 1 set 1 gnd 1 2 3 4 8 7 6 5 v+ out 2 set 2 hyst 2 data sheet june 2004 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ge/intersil 1983-84, ge/rca 1987, harris corp. 1994, intersil americas inc. 1999, 2004. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 absolute maximum rati ngs thermal information supply voltage (note 2) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +18v output voltages out1 and out2 . . . . . . . . . . . . . . . . . -0.3v to 18v (with respect to gnd) (note 2) output voltages hyst1 and hyst2 . . . . . . . . . . . . . . -0.3v to +18v (with respect to v+) (note 2) input voltages set1 and set2 . . . . . (gnd -0.3v) to (v+ v- +0.3v) (note 2) maximum sink output out1 and out2 . . . . . . . . . . . . . . . . . 25ma maximum source output current hyst1 and hyst2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25ma operating conditions temperature range ICL7665Sc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 c to 70 c ICL7665Si . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40 c to 85 c thermal resistance (typical, note 1) ja ( c/w) pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 maximum junction temperature (plastic) . . . . . . . . . . . . . . . . 150 c maximum junction temperature (cerdip). . . . . . . . . . . . . . . 175 c maximum storage temperature range . . . . . . . . . . . -65 c to 150 c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 c (soic - lead tips only) caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. ja is measured with the component mount ed on an evaluation pc board in free air. 2. due to the scr structure inherent in the cmos process used to fabricate these devices, connecti ng any terminal to voltages gr eater than (v+ +0.3v) or less than (gnd - 0.3v) may cause destructive device latchup. fo r these reasons, it is recommended that no inputs from external sources not operating from the same power supply be applied to th e device before its supply is established, and that in multipl e supply systems, the supply to the ICL7665S be turned on first. if this is not possible, current into inputs and/or outputs must be limited to 0.5ma and voltages must not exceed those defined above. electrical specifications the specifications below are applicable to both the ICL7665S and ICL7665Sa. v+ = 5v, t a = 25 c, test circuit figure 7. unless otherwise specified parameter symbol test conditions min typ max units operating supply voltage v+ ICL7665S t a = 25 c1.6-16v 0 c t a 70 c1.8-16v -25 c t a 85 c1.8-16v ICL7665Sa 0 c t a 70 c1.8-16v -25 c t a 85 c1.8-16v supply current i+ gnd v set1 , v set2 v+, all outputs open circuit 0 c t a 70 c v+ = 2v - 2.5 10 a v+ = 9v - 2.6 10 a v+ = 15v - 2.9 10 a -40 c t a 85 c v+ = 2v - 2.5 10 a v+ = 9v - 2.6 10 a v+ = 15v - 2.9 10 a input trip voltage v set1 ICL7665S 1.20 1.30 1.40 v v set2 1.20 1.30 1.40 v v set1 ICL7665Sa 1.275 1.30 1.325 v v set2 1.275 1.30 1.325 v temperature coefficient of v set ? v set ? t ICL7665S - 200 - ppm ICL7665Sa - 100 - ppm supply voltage sensitivity of v set1 , v set2 ? v set ? v s r out1 , r out2 , r hyst1 , r 2hyst2 = 1m ?, 2v v+ 10v -0.03-%/v ICL7665S
3 output leakage currents of out and hyst i olk v set = 0v or v set 2v - 10 200 na i hlk - -10 -100 na i olk v+ = 15v, t a = 70 c - - 2000 na i hlk - - -500 na output saturation voltages v out1 v set1 = 2v, i out1 = 2ma v+ = 2v - 0.2 0.5 v v+ = 5v - 0.1 0.3 v v+ = 15v - 0.06 0.2 v output saturation voltages v hyst1 v set1 = 2v, i hyst1 = -0.5ma v+ = 2v - -0.15 -0.30 v v+ = 5v - -0.05 -0.15 v v+ = 15v - -0.02 -0.10 v output saturation voltages v out2 v set2 = 0v, i out2 = 2ma v+ = 2v - 0.2 0.5 v v+ = 5v - 0.15 0.3 v v+ = 15v - 0.11 0.25 v output saturation voltages v hyst2 v set2 = 2v v+ = 2v, i hyst2 = -0.2ma - -0.25 -0.8 v v+ = 5v, i hyst2 = -0.5ma - -0.43 -1.0 v v+ = 15v, i hyst2 = -0.5ma - -0.35 -0.8 v v set input leakage current i set gnd v set v+ - 0.01 10 na ? input for complete output change ? v set r out = 4.7k ? , r hyst = 20k ? , v out lo = 1% v+, v out hi = 99% v+ ICL7665S - 1.0 - mv ICL7665Sa - 0.1 - mv difference in trip voltages v set1 - v set2 r out , r hyst = 1mw - 5 50 mv output/hysteresis difference r out , r hyst = 1mw ICL7665S - 1-mv ICL7665Sa - 0.1 - mv notes: 3. derate above 25 c ambient temperature at 4mw/ c. 4. all significant improvements over th e industry standard icl7665 are highlighted. electrical specifications the specifications below are applicable to both the ICL7665S and ICL7665Sa. v+ = 5v, t a = 25 c, test circuit figure 7. unless otherwise specified (continued) parameter symbol test conditions min typ max units ac electrical specifications parameter symbol test conditions min typ max units output delay times input going hi t so1d v set switched between 1.0v to 1.6v r out = 4.7k ? , c l = 12pf r hyst = 20k ? , c l = 12pf -85- s t sh1d -90- s t so2d -55- s t sh2d -55- s input going lo t s o1d v set switched between 1.6v to 1.0v r out = 4.7k ? , c l = 12pf r hyst = 20k ? , c l = 12pf -75- s t s h1d -80- s t s o2d -60- s t s h2d -60- s ICL7665S
4 functional block diagram output rise times t o1r v set switched between 1.0v to 1.6v r out = 4.7k ? , c l = 12pf r hyst = 20k ? , c l = 12pf -0.6- s t o2r -0.8- s t h1r -7.5- s t h2r -0.7- s output fall times t o1f v set switched between 1.0v to 1.6v r out = 4.7k ? , c l = 12pf r hyst = 20k ? , c l = 12pf -0.6- s t o2f -0.7- s t h1f -4.0- s t h2f -1.8- s ac electrical specifications (continued) parameter symbol test conditions min typ max units ref set1 set2 + - + - v+ hyst2 hyst1 out2 out1 gnd conditions (note 5) v set1 > 1.3v, out1 switch on, hyst1 switch on v set1 < 1.3v, out1 switch off, hyst1 switch off v set2 > 1.3v, out2 switch off, hyst2 switch on v set2 < 1.3v, out2 switch on, hyst2 switch off note: 5. see electrical specificat ions for exact thresholds. ICL7665S
5 typical performance curves figure 1. out1 saturation voltage as a function of output current figure 2. out2 saturation voltage as a function of output current figure 3. hyst1 output saturation voltage vs hyst1 output current figure 4. hyst2 output saturation voltage vs hyst2 output current figure 5. supply current as a function of ambient temperature figure 6. supply current as a function of supply voltage voltage saturation (v) 2.0 1.5 1.0 0.5 0 0 5 10 15 20 i out out1 (ma) v+ = 2v v+ = 5v v+ = 15v v+ = 9v 0 5 10 15 20 2.0 1.5 1.0 0.5 0 voltage saturation (v) i out out2 (ma) v+ = 2v v+ = 5v v+ = 9v v+ = 15v -20 -16 -12 -8 -4 0 0 -0.4 -0.8 -1.2 -1.6 -2.0 hyst1 output saturation voltage (v) hyst1 output current (ma) v+ = 15v v+ = 9v v+ = 5v v+ = 2v t a = 25c -5.0 -4.0 -3.0 -2.0 -1.0 0 0 -1.0 -2.0 -3.0 -4.0 -5.0 hyst2 output current (ma) hyst2 output saturation voltage (v) t a = 25c v+ = 15v v+ = 9v v+ = 5v v+ = 2v v+ = 2v v+ = 15v v+ = 9v 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -25 0 +20 +40 +60 ambient temperature (c) supply current ( a) 0v v set1 , v set2 v+ 0v v set1 , v set2 v+ 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 2 4 6 810121416 supply voltage (v+) supply current ( a) t a = -20c t a = 25c t a = 70c ICL7665S
6 detailed description as shown in the functional diagram, the ICL7665S consists of two comparators which compare input voltages on the set1 and set2 terminals to an internal 1.3v bandgap reference. the outputs from the two comparators drive open-drain n-channel transistors for out1 and out2, and open-drain p-channel transistors for hyst1 and hyst2 outputs. each section, the undervoltage detector and the overvoltage detector, is independent of the other, although both use the internal 1.3v refe rence. the offset voltages of the two comparators will normally be unequal so v set1 will generally not quite equal v set2 . the input impedance of the set1 and set2 pins are extremely high, and for most practical applications can be ignored. the four outputs are open-drain mos transistors, and when on behave as low resistance switches to their respective supply rails. this mi nimizes errors in setting up the hysteresis, and maximizes the output flexibility. the operating currents of the bandgap reference and the comparators are around 100na each. precautions junction isolated cmos devi ces like the ICL7665S have an inherent scr or 4-layer pn pn structure distributed throughout the die. under certain circumstances, this can be triggered into a potentially destructive high current mode. this latchup can be triggered by forward-biasing an input or output with respect to the po wer supply, or by applying excessive supply voltages. in very low current analog circuits, such as the ICL7665S, this scr can also be triggered by applying the input power supply extremely rapidly (?instantaneously?), e.g., through a low impedance battery and an on/off switch with short lead lengths. the rate-of-rise of the supply voltage can exceed 100v/ s in such a circuit. a low impedance capacitor (e.g., 0.05 f disc ceramic) between the v+ and gnd pins of the ICL7665S can be used to reduce the rate-of-rise of the supply voltage in battery applic ations. in line operat ed systems, the rate-of- rise of the supply is limited by other considerations, and is normally not a problem. if the set voltages must be applied before the supply voltage v+, the input current should be limited to less than 0.5ma by appropriate external resistors, usually required for voltage setting anyway. a similar precaution should be taken with the outputs if it is likely that they will be driven by other circuits to levels outside the supplies at any time. simple threshold detector figure 9 shows the simplest connection of the ICL7665S for threshold detection. from the gr aph 9b, it can be seen that at low input voltage out1 is off, or high, while out2 is on, or low. as the input rise s (e.g., at power-on) toward v nom (usually the eventual operating voltage), out2 goes high on reaching v tr2 . if the voltage rises above v nom as much as v tr1 , out1 goes low. the equation giving v set1 and v set2 are from figure 9a: since the voltage to trip each comparator is nominally 1.3v, the value v in for each trip point can be found from and 1 2 3 4 8 7 6 5 out1 hyst1 set1 gnd v+ out2 set2 hyst2 input hyst2 out2 out1 v+ 20 k ? 12 pf 12 pf 12 pf 12 pf 20 k ? 4.7k ? hyst1 4.7 k ? 1.0v 1.6v figure 7. test circuits v set1 , v set2 t so1 d t o1f t s o1d t o1 r t sh1 d t h1 r t s h1 d t h1 f t so2 d t o2 r t s o2 d t o2 f t sh2 d t h2 r t s h2 d t h2 f 1.6v 1.0v v+ gnd gnd gnd gnd (5v) v+ (5v) v+ (5v) v+ (5v) input out1 hyst1 out2 hyst2 figure 8. switching waveforms v set1 v in r 11 r 11 r 21 + () ------------------------------- - = v set2 v in r 12 r 12 r 22 + () ------------------------------- - = v tr1 v set1 r 11 r 21 + () r 11 --------------------------------- - 1.3 r 11 r 21 + () r 11 --------------------------------- - for detector 1 = = v tr2 v set2 r 12 r 22 + () r 12 --------------------------------- - 1.3 r 12 r 22 + () r 12 --------------------------------- - for detector 2 = = ICL7665S
7 either detector may be used alone, as well as both together, in any of the circuits shown here. when v in is very close to one of the trip voltage, normal variations and noise may cause it to wander back and forth across this level, leading to erratic output on and off conditions. the addition of hyst eresis, making the trip points slightly different for rising and falling inputs, will avoid this condition. threshold detector with hysteresis figure 10a shows how to set up such hysteresis, while figure 10b shows how the hysteresis around each trip point produces switching action at different points depending on whether v in is rising or falling (the arrows indicated direction of change. the hyst outputs are basically switches which short out r 31 or r 32 when v in is above the respective trip point. thus if the input voltage rises from a low value, the trip point will be controlled by r 1n , r 2n , and r 3n , until the trip point is reached. as this value is passed, the detector changes state, r 3n is shorted out, and the trip point becomes controlled by only r 1n and r 2n , a lower value. the input will then have to fall to this new point to restore the initial comparator state, but as soon as this occurs, the trip point will be raised again. an alternative circuit for obtaining hysteresis is shown in figure 11. in this configuration, the hyst pins put the extra resistor in parallel with the upper setting resistor. the values of the resistors differ, but the action is essentially the same. the governing equations are given in table 1. these ignore the effects of the resistance of the hyst outputs, but these can normally be neglected if the resistor values are above about 100k ? . out1 set1 set2 out2 v+ r 21 r p2 v in r p1 r 22 r 11 r 12 figure 9a. circuit configuration off v out on v tr2 v nom v tr1 detector 2 detector 1 figure 9b. transfer characteristics figure 9. simple threshold detector hyst1 set1 set2 hyst2 v+ v in out1 out2 r 31 r 32 r 12 r 11 r 21 r 22 overvoltage overvoltag e figure 10a. circuit configuration v l2 v u2 v l1 v u1 on out off v nom detector 2 detector 1 v in figure 10b. transfer characteristics figure 10. threshold detector with hysteresis v tr2 v set2 r 12 r 22 + () r 12 --------------------------------- - 1.3 r 12 r 22 + () r 12 --------------------------------- - for detector 2 = = ICL7665S
8 applications single supply fault monitor figure 12 shows an over/under voltage fault monitor for a single supply. the overvoltage trip point is centered around 5.5v and the undervoltage trip point is centered around 4.5v. both have some hysteresis to prevent erratic output on and off conditions. the two outputs are connected in a wired or configuration with a pullup resistor to generate a power ok signal. multiple supply fault monitor the ICL7665S can simultaneously monitor several supplies when connected as shown in figure 13. the resistors are chosen such that the sum of the currents through r 21a , r 21b , and r 31 is equal to the current through r 11 when the two input voltage are at the desired low voltage detection point. the current through r 11 at this point is equal to 1.3v/r 11 . the voltage at the v set input depends on the voltage of both supplies being monitored. the trip voltage of one supply while the other supply is at the nominal voltage will be different that the trip voltage when both supplies are below their nominal voltages. the other side of the ICL7665S can be used to detect the absence of negative supplies. the trip points for out1 depend on both the negative supply voltages and the actual voltage of the +5v supply. table 1. set-point equations no hysteresis overvoltage v trip = r 11 + r 21 r 11 x v set1 overvoltage v trip = r 12 + r 22 r 12 x v set2 hysteresis per figure 10a v u1 = r 11 + r 21 + r31 r 11 x v set1 overvoltage v trip v l1 = r 11 + r 21 r 11 x v set1 v u2 = r 12 + r 22 + r 32 r 12 x v set2 undervoltage v trip v l2 = r 12 + r 22 r 12 x v set2 hysteresis per figure 11 v u1 = r 11 + r 21 r 11 x v set1 overvoltage v trip v l1 = r 11 + r 21 r 31 r 21 + r 31 x v set1 r 11 v u2 = r 12 + r 22 r 12 x v set2 overvoltage v trip v l2 = r 12 + r 22 r 32 r 22 + r 32 x v set2 r 12 out1 set1 set2 out2 v+ r 21 r p v in r p r 22 r 11 r 12 hyst1 hyst2 r 31 r 32 figure 11. an alternative hysteresis circuit hyst1 v set1 v set2 hyst2 v+ out1 out2 324k ? 13m ? 5% 100k ? 249k ? 7.5m ? 5% +5v supply power ok 100k ? 1m ? v+ open voltage detector v u = 5.55v v l = 5.45v open voltage detector v u = 4.55v v l = 4.45v r 22 r 32 r 12 r 11 r 31 r 21 figure 12. fault monitor for a single supply ICL7665S
9 combination low battery warning and low battery disconnect when using rechargeable batt eries in a system, it is important to keep the batteri es from being over discharged. the circuit shown in figure 14 provides a low battery warning and also disconnects the low battery from the rest of the system to prevent damage to the battery. out1 is used to shutdown the icl7663s when the battery voltage drops to the value where the load should be disconnected. as long as v set1 is greater than 1.3v, out1 is low, but when v set1 drops below 1.3v, out1 goes high shutting off the icl7663s. out2 is used for low battery warning. when v set2 is greater than 1.3v, out2 is high and the low battery warning is on. when v set2 drops below 1.3v, out2 is low and the low battery warning goes off. the trip voltage for low battery warning can be set higher than the trip voltage for shutdown to give advance low battery warning before the battery is disconnected. power fail warning and powerup/powerdown reset figure 15 shows a power fail warning circuit with powerup/powerdown reset. when the unregulated dc input is above the trip point, out1 is low. when the dc input drops below the trip point, out1 shuts off and the power fail warning goes high. the voltage on the input of the 7805 will continue to provide 5v out at 1a until v in is less than 7.3v, this circuit will provid e a certain amount of warning before the 5v output begins to drop. the ICL7665S out2 is used to prevent a microprocessor from writing spurious data to a cmos battery backup memory by causing out2 to go low when the 7805 5v output drops below the ICL7665S trip point. figure 13. multiple supply fault monitor hyst1 v set1 v set2 hyst2 v+ out1 out2 274k ? r 21 100k ? 22 power ok 301 r 11 +5v -15v -5v m ? k ? 787 k ? +5v 1m ? 1.02m ? r 21a r 21b 22m ? 49.9k ? +5v +15v hyst1 set1 set2 hyst2 v+ out1 out2 r 31 r 32 r 12 r 11 r 21 r 22 gnd + - low battery shutdown 1m ? v+ out1 shutdown v set out2 v+ gnd 1m ? low battery warning sense 100 ? +5v 1a icl7663s ICL7665S figure 14. low battery warning and low battery disconnect ICL7665S
10 simple high/low temperature alarm figure 16 illustrates a simple high/low temperature alarm which uses the ICL7665S with an npn transistor. the voltage at the top of r 1 is determined by the v be of the transistor and t he position of r 1 ?s wiper arm. this voltage has a negative temperature coefficient. r 1 is adjusted so that v set2 equals 1.3v when the npn transistor?s temperature reaches the temperature selected for the high temperature alarm. when this occurs, out2 goes low. r 2 is adjusted so that v set1 equals 1.3v when the npn transistor?s temperature reac hes the temperature selected for the low temperature alarm. when the temperature drops below this limit, out1 goes low. ac power fail and brownout detector figure 17 shows a circuit that detects ac undervoltage by monitoring the secondary side of the transformer. the capacitor, c 1 , is charged through r 1 when out1 is off. with a normal 100 vac input to the transformer, out1 will discharge c 1 once every cycle, approximately every 16.7ms. when the ac input voltage is reduced, out1 will stay off, so that c 1 does not discharge. when the voltage on c 1 reaches 1.3v, out2 turns off and the power fail warning goes high. the time constant, r 1 c 1 , is chosen such that it takes longer than 16.7ms to charge c 1 1.3v. hyst1 v set1 v set2 hyst2 v+ out1 out2 5.86k ? 130k ? backup battery 7805 5v regulator unregulated dc input 1m ? 22m ? 2.2m ? 1m ? 715k ? 1m ? reset or write enable power fail warning 470 f 4700 f ICL7665S figure 15. power fail warning and powerup/powerdown reset ICL7665S
11 hyst1 v set1 v set2 hyst2 v+ out1 out2 22k ? 1.5m ? 22m ? 1m ? 27k ? r 4 r 5 v+ 1m ? r 7 r 2 r 6 alarm signal for driving leds, bells, etc. low temperature limit adjust +- 5v 470k ? r 3 temperature sensor (general purpose npn transistor) 10k ? high temperature limit adjust r 1 ICL7665S figure 16. simple high/low temperature alarm 110vac 60hz 20v centered tapped trans. 4700 f 601k ? 100k ? hyst1 v set1 v set2 hyst2 out1 out2 1m ? 1m ? 7805 5v regulator 5v, 1a c 1 r 1 1m ? +5v power fail warning ICL7665S figure 17. ac power fail and brownout detector ICL7665S
12 ICL7665S dual-in-line plastic packages (pdip) c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a 1 -a- 0.010 (0.25) c a m bs notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the inch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the ?mo se ries symbol list? in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are m easured with the package seated in jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protru- sions. mold flash or protrusi ons shall not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be per- pendicular to datum . 7. e b and e c are measured at the lead tips with the leads uncon- strained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- e8.3 (jedec ms-001-ba issue d) 8 lead dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.210 - 5.33 4 a1 0.015 - 0.39 - 4 a2 0.115 0.195 2.93 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.045 0.070 1.15 1.77 8, 10 c 0.008 0.014 0.204 0.355 - d 0.355 0.400 9.01 10.16 5 d1 0.005 - 0.13 - 5 e 0.300 0.325 7.62 8.25 6 e1 0.240 0.280 6.10 7.11 5 e 0.100 bsc 2.54 bsc - e a 0.300 bsc 7.62 bsc 6 e b - 0.430 - 10.92 7 l 0.115 0.150 2.93 3.81 4 n8 89 rev. 0 12/93
13 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com ICL7665S small outline plast ic packages (soic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. m8.15 (jedec ms-012-aa issue c) 8 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.1890 0.1968 4.80 5.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n8 87 0 o 8 o 0 o 8 o - rev. 0 12/93

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